Typical electronic logic systems today use clocked Boolean binary logic circuits. Such binary circuits express two values as separate voltages on a single signal line, such as numeric values ZERO and ONE, or logical TRUE and FALSE. Most often, a ground voltage potential represents numeric ZERO or logic FALSE, and a second voltage (e.g., +5 volts) represents numeric ONE or logic TRUE. The most commonly used logic systems perform Boolean logic operations on binary signals, such as AND, OR, and NOT operations. A signal format that uses a single signal line to represent binary values for use with Boolean logic will be referred to here as "Boolean binary" format.
Clocked Boolean logic (CBL) circuits are Boolean logic circuits that use clock signals to regulate the timing of signal processing. For example, a clocked Boolean logic circuit might present input signals to a circuit on the rising edge of a clock, and latch the output of the circuit on the falling edge of the clock. Such use of a clock allows the input signals time to propagate through the circuit, and (if properly designed) ensures that the circuit outputs have settled to final values before sampling the result. Clocks tend be highly regulated to have a fixed frequency (and thus a fixed period), by deriving their periods from a crystal or other oscillator. If the clock period is shorter than signal propagation delay through the circuit, the output might not be valid at the sampling time, and potentially invalid data will be latched.
A First-In-First-Out(FIFO) buffer is a memory circuit characterized by the order in which data may be stored and recovered. Data may be read from a FIFO buffer only in the same order in which it was stored. For example, the first data read from a FIFO buffer is always the first data that was stored (hence the name "first-in-first-out"). A FIFO buffer can also be characterized by two size properties. The width (or "word size") of a FIFO buffer describes the amount of data that can be stored or read at one time. The depth describes the total amount of information that can be stored (often quoted as a number of words).
In clocked FIFO buffers, one or more clock signals regulate the timing of read and write operations, as well as internal operations. When a single clock is used, the input and output rates are identical, and data propagates through the buffer with a fixed delay. Internally, the clock signal regulates movement of data through a series of storage locations so that the contents of all storage locations advance simultaneously. If the clock rate exceeds the maximum operating speed of the internal circuits, an internal storage location might latch a value before receiving new data from a prior location. Furthermore, the circuit associated with a storage location could oscillate or become metastable.
Typically, internal circuitry is designed to operate at conservative clock speeds that allow some margin between the clock period and the worst case delays in the internal circuitry. Such margin avoids certain timing problems, but guarantees that many or all parts of the circuit operate at less than the maximum possible speed.
In other clocked FIFO buffers, separate read and write clocks regulate the writing and reading processes. The read and write clocks determine the read and write data rates, respectively, which may be different. Overflow may occur when an external circuit attempts to write data to a full buffer. Under flow may occur when an external circuit attempts to read data from an empty buffer.
It is relatively simple to build synchronous FIFO buffers for use between two external circuits if both external circuits use the same clock or synchronized clocks. However, FIFO buffers have proven relatively harder to design and control reliably for systems operating in two different and non-synchronous clock domains. Such a FIFO must accommodate (1) irregularities in the availability of data, and (2) differences in the basic clocking systems. Thus, in two-clock FIFO buffer design, the form of clock used within a FIFO and its control logic is an important factor that absorbs substantial design resources and time.
It is desirable to have a complete family of FIFO designs that are readily available, easily scale able, and do not suffer from timing problems or metastability. It would be possible to maintain a large library of commonly-used and tested FIFO designs for a wide variety of purpose. However, it would be nearly impossible to predict and account for all such uses. Therefore, a new (or modified) design would have to be produced for each application then rigorously tested.